1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a method for fabricating a semiconductor memory, in which a resistive layer is formed of a material identical to a material of a cell plug layer at a time of formation of the cell plug layer and an area of a salicide layer on the cell plug layer is formed larger, for simplifying the fabrication process and securing an adequate fabrication allowance.
2. Background of the Related Art
A related art semiconductor memory will be explained with reference to the attached drawings. FIGS. 1A.about.1E illustrate sections showing the steps of a related art method for fabricating a semiconductor memory.
Referring to FIG. 1A, the related art method for fabricating a semiconductor memory starts with forming a device isolating layer 2 in a device isolating region of a semiconductor substrate 1 by an STI (Shallow Trench Isolation) and forming a gate oxide film on an entire surface. A polysilicon layer for forming a gate electrode and an insulating material layer ate formed on the gate oxide film 3 in succession, and subjected to selective patterning by photolithography, to form a polygate layer 4a and a cap insulating layer 4b. In this instance, a gate electrode layer (a wordline) 6 of a cell transistor is formed in a cell region, and a gate electrode layer 7 of a driver transistor used in input/output of data is formed in a peripheral circuit region. The polygate layer 4a for forming a gate electrode and the cap insulating layer 4b are patterned with a dummy pattern in a portion of the peripheral circuit region, for use as a restrictive layer 5 for forming a circuit. Though not shown in the drawing, there are impurity regions for use as source/drain form in surfaces of the semiconductor substrate 1 on both sides of the gate electrode. Then, as shown in FIG. 1B, a material layer for forming gate sidewalls is formed on an entire surface inclusive of the cell region and the peripheral circuit region, a mask layer is formed of a material, such as photoresist (not shown) on the device isolation region, and etched back to form gate sidewalls 8 at sides of the gate electrode layer 6 in the cell region. As shown in FIG. 1C, the photoresist layer used as the mask layer in the etch back is removed. A material layer for forming a plug, for example, a polysilicon layer is formed on an entire surface, and etched back, to form a polyplug layer 9 which is in contact with the impurity regions and stuffing spaces between the gate electrodes 6 (but insulated from the gate electrode layer by the gate sidewalls). Then, as shown in FIG. 1D, the cell region is masked by a material layer of photoresist and the like, a material layer for forming sidewalls is formed on an entire surface of the peripheral circuit region, and etched back, to form gate sidewalls 10. In this instance, in order not to leave the material layer for forming gate sidewalls, an overetch is made in the etch back, to etch portions of the device isolation layer 2 and the cap insulation layer 4b. As shown in FIG. 1E, a salicide layer 10 is formed on the polyplug layer 9 and the impurity region in the device isolating region, and an ILD (Inter Layer Dielectric) layer 11 is formed on an entire surface. Then, the ILD layer 11 is etched selectively until the salicide layer 10 is exposed, to form a bitline contact hole 12.
In the forgoing related art method for fabricating a semiconductor memory, the polysilicon layer is patterned, to form the wordline as well as the resistive layer 5 in the peripheral circuit region at the same time. Then, the polyplug layer 9 is deposited and the salicide layer is formed, for improving gluing with a bitline formed later and electrical characteristics such as a contact resistance.
However, the aforementioned related art semiconductor memory has the following problems.
The use of polysilicon as a material of the wordline puts limitation in a signal transmission speed, making implementation of a high speed memory difficult. In order to solve the problem of operation speed, the material of the wordline and the bitline is replaced with metal. However, the wordline and the bitline formed of metal requires formation of the resistive layer of polysilicon additionally, resulting in entire fabrication process complicated.
The formation of salicide layer after deposition of the polyplug layer puts limitation on an area of the contact hole, and limitation on a salicide area caused by an alignment error, even within a tolerance in formation of the bitline contact hole it deteriorates a contact performance.
The overetch occurring in contact hole formation is liable to cause short with a gate electrode layer.